1. Field of the Invention
The present invention relates to a semiconductor substrate having a surface layer structure and more particularly to a semiconductor substrate made of a GaAS or Ga, As-containing ternary or more alloy or mixed crystal having a surface layer structure on which a metal or insulator can be provided. Further, the present invention relates to a semiconductor device having a semiconductor substrate having such a surface layer structure. The present invention also relates to a method of fabricating a semiconductor substrate and a method of fabricating a semiconductor device having a semiconductor substrate with such a surface layer structure.
2. Description of the Prior Art
Periodicity of a crystal is lost on the surface of a semiconductor and one or more states for carriers (electrons and holes) tend to appear in the vicinity of the surface of the semiconductor. These states are called surface (or interface) states. Since surface states have a great influence on the performance and reliability of the semiconductor devices, so-called passivation or inactivation of the surface is usually carried out, whereby the surface of the semiconductor is covered with an insulator layer to appropriately terminate unbonded dangling bonds to prevent the occurrence of surface states in, for example, the forbidden band, thereby rendering the surface inactive visa vis the external atmosphere surrounding the semiconductor. In the case where a surface (interface) state with an energy level in the forbidden band does exist in the vicinity of an area a semiconductor covered with a native oxide or passivated layer, that surface (interface) state catches or releases carriers (electrons or holes) in the band, with the result that excessive carriers, if any, in the vicinity of the surface, cause recombination of electrons with holes, thus having a great influence on the behavior or performance of the semiconductor device.
On the surface of a III-V compound semiconductor such as GaAs, a large surface recombination velocity is quite often observed. This presents an obstacle to fabricating actual semiconductor devices having characteristics as close as possible to ideal ones. This is considered to be attributable to the existence of surface states in high densities on the surfaces of the semiconductor. Accordingly, various surface passivation techniques have been proposed in order to suppress the occurrence of high density surface states.
For example, a surface structure has been known in which the surface of a GaAs semiconductor is covered with a surface passivation atom such as sulfur (S) or phosphorus (P) to form a monoatomic layer or thicker overcoat. The term "surface passivation" as used herein refers to improvements in electrical characteristics such as the reduction in the rate of recombination of carriers on the surface of a semiconductor, i.e., the reduction in leakage current in pn junctions, or the reduction in the surface (or interface) state density to relax the pinning of the Fermi level on the surface.
FIG. 1 is a cross sectional view showing a GaAs semiconductor substrate having a conventional surface layer structure. FIG. 2 is an energy band diagram for the cross section of the semiconductor device having the surface layer structure as shown in FIG. 1. In FIG. 1, reference numeral 10 denotes a semiconductor substrate having a surface layer structure, 12 denotes a GaAs semiconductor substrate, 12A and 12B denote front and back facets or surfaces of the semiconductor substrate, respectively, and 15 denotes a surface passivation monolayer. The GaAs semiconductor substrate 12 has a layer or overcoat of S or P of a thickness of about one atom or more on the facet 12A on the front side of the semiconductor. FIG. 2 shows an energy distribution in the direction from the front facet 12A toward the back facet 12B where C, V and IS stand for a conduction band, a valence band and surface (or interface) states, respectively, CBM and VBM stand for a conduction band minimum and a valence band maximum, respectively, Ev is a maximum of the valence band of the substrate, and FB stands for a forbidden band of the substrate 12. In the surface layer structure as shown in FIG. 1, the surface states, IS exist exposedly or unresonantly in the forbidden band which is between the conduction band minimum, CBM and the valence band maximum, VBM as shown in FIG. 2. Note that on actual surfaces, the Fermi level is fixed to surface states. This phenomenon is called pinning by surface states. Due to pinning, CBM and VBM increase toward the left hand side in FIG. 2 under no external voltage. That is, on the actual surfaces, CBM and VBM are not linear nor horizontal (like those shown in FIG. 2), but, for example, go up or ascend toward the left hand side in n-type semiconductors. However, for the sake of simplicity of explanation and in order to clearly illustrate that surface states are in the forbidden band or band gap, CBM and VBM potentials are each illustrated as horizontal, and relations of CBM and VBM with the Fermi level are omitted from the following explanation.
To realize the aforementioned surface layer structure, various methods have been proposed. For example, a wet treatment is known in which a GaAs wafer is immersed in an ammonium polysulfide solution as described in, for example, Nannichi et al., JJAP, vol. 27, p. L2367 (1988). Also, a dry treatment using H.sub.2 S gas is known. For the P overcoat, a method has been known in which GaAs is exposed in a plasma of phosphine (PH.sub.3) gas as described in Sugino, et al., Defect Control in Semiconductor, p. 849, Elsevier Science Publishers B.V., North-Holland (1990).
Among the aforementioned methods, the S overcoats have been experimentally demonstrated to be generally effective for surface passivation of GaAs. For example, the provision of an S overcoat is known to increase the intensity of photoluminescence (hereafter, sometimes referred to simply as "PL intensity") by 5 to 8 times and decreased interface state density to 1.2.times.10.sup.11 cm.sup.-2 eV.sup.-1 (cf. Fan et al., JJAP, vol. 28, p. L2255 (1989)).
Provision of a P overcoat on the surface of GaAs was shown to strengthen dependence of the height of barrier of a Schottky contact on the work function as compared with non-passivated surface (cf. Sugino, et al., Defect Control in Semiconductor, p. 849, Elsevier Science Publishers B.V., North-Holland (1990)), confirming relaxation of the pinning of Fermi level at the surface state. However, the P overcoat remained less effective than the S overcoat.
On the other hand, in the application to devices, semiconductor chips such as P-coated GaAs or S-coated compound semiconductor chips have been protected by depositing an insulator layer such as a layer of silicon oxide on the surface thereof. More specifically, in hereto bipolar transistors (HBT's), the provision of an S layer on pn junctions resulted in an increase in the current gain (cf, for example, Shikada, et al., 1990 Autumn Meeting of Japan Society of Applied Physics, Report No. 26a-SQ-20), or its provision on a reflecting facet of a laser resulted in improvement in the high output properties of the laser (cf., Sasaki, et al., 1990 Spring Meeting of Japan Society of Applied Physics, Report No. 28a-SA-20).
On the other hand, it has also been reported that the provision of an S overcoat caused the pinning of the Fermi level by the surface state (cf. Spindt, et al., APL, vol. 55 (16), p. 1653 (1989)).
Further, a method has been proposed in which a material having a band gap wider than GaAs, such as AlGaAs, is epitaxially grown thick (about 200 Angstroms or more) on the surface of a GaAs semiconductor to suppress high density surface states present at the surface of the semiconductor (cf., J. I. Pankove, et al., J. of Electronic Materials, 12, p. 359 (1983)).
FIG. 3 is a schematic cross sectional view showing a semiconductor substrate with the aforementioned thick conventional surface layer structure. In FIG. 3, reference numerals 10, 12, and 12A are the same as in FIG. 1, and 13 is a wide band gap material layer, and 13A is a surface of the wide band gap material layer 13. Symbol D indicates distance from the surface 13A of the wide band gap material layer, and symbol D.sub.1 indicates the distance of the surface (interface) 12A from the surface 13A. In the arrangement shown in FIG. 3, the wide band gap material layer 13 in place of the covering layer 16 in FIG. 1 is provided on the substrate 12.
FIG. 4 is a schematic energy band diagram of the cross section of the conventional GaAs semiconductor substrate shown in FIG. 3, with plotting energy versus distance from the surface 13A of the wide band gap material layer 13 opposing the front facet 12A of the GaAs semiconductor 12 toward the back facet 12B (not shown) of the semiconductor 12. In FIG. 4, CBM.sub.1 indicates the conduction band minimum of the semiconductor substrate 12, CBM.sub.02 indicates the conduction band minimum of the wide band gap material layer 13, VBM.sub.1 indicates the valence band maximum of the substrate 12, and VBM.sub.02 indicates the valence band maximum of the wide band gap material layer 13, Ec.sub.1 indicates the energy of conduction band minimum of the substrate 12, Ec.sub.2 indicates the energy of the conduction band minimum of the wide band gap material layer 13, Ev.sub.1 indicates the energy of the valence band maximum of the substrate 12, Ev.sub.2 indicates the energy of the valence band maximum of the wide band gap material layer 13, and D.sub.1 indicates the distance of the interface 12A from the surface 13A of the wide band gap material layer 13. With respect to the valence band maximum VBM.sub.1 and conduction band minimum CBM.sub.1 of the GaAs semiconductor, the valence band maximum VBM.sub.2 and conduction band minimum CBM.sub.2 of the wide band gap material have energy level gaps, .DELTA.Ev (=E.sub.v1 -E.sub.v2), and .DELTA.Ec (=E.sub.c2 -E.sub.c1), respectively, thus forming a thick potential barrier. The thick potential barrier prevents carriers (electrons and holes) from approaching the surface of the semiconductor. Therefore, no surface recombination occurs wherever surface states exist in the surface layer 13A of the wide band gap material 13.
However, the conventional method of providing a thick layer of a wide band gap material such as S or P on the surface of a semiconductor, is not applicable so far as currently adopted structural design fabrication techniques are concerned. If one were to forcibly use such a conventional method, a supply of electrons would be produced from the thick wide gap material layer, and the resulting semiconductor device would have to be classified (from the viewpoint of the principle of operation) as a high electron mobility transistor (HEMT), and HEMTs require high technology techniques for fabricating integrated circuits.
In order to obtain actual devices having characteristics as close as possible to ideal ones, there has been a keen desire for further improvement in the suppression of high density surface states existing in the vicinity of the surface of the semiconductor.